1. Field of the Invention
The invention relates to a semiconductor packaging structure, and more particularly, to a face-to face multi-chip package.
2. Description of the Related Art
As the technology of semiconductor fabrication grows more and more advanced, the relevant techniques have to be further developed to coordinate the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique is used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage. The third stage is the packaging process. It is now a leading trend for fabricating a device or an electronic product with a thin, light, and small dimension, that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package, multi-chip module (MCM) have been developed to obtain a high integration. The development of the fabrication technique with a line width of 0.18 .mu.m has evoked a great interest and intensive research to further decrease the package volume. It is thus one of the very important package techniques to arrange more than one chip into a single package. In a multi-chip package, chips of processor, memory, including dynamic random access memory (DRAM) and flash memory, and logic circuit can be packed together in a single package to reduce the fabrication cost and the packaging volume. Furthermore, the signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology may also be applied to a multi-chip system with variable functions and operation frequencies, for example,
1. A system comprises memory chips, microprocessors, resistors, capacitors, and inductors. PA1 2. A system comprises memory chips (DRAM), logic circuit chips, and memory chips (Flash memory), PA1 3. A system comprises analog chips, logic circuit chips, memory chips (including DRAM, SRAM, Flash memory), resistor, capacitor, and inductor.
In FIG. 1, a conventional multi-chip module is shown. A multi-level printed circuit board (PCB) is typically applied as a substrate of the to the carrier of a multi-chip module. More than one chip 12 are adhered on the substrate 10 by insulation glue 14. The bonding pads on the chip 12 are electrically connected to the terminals on the substrate 10 by conductive wires 16. In addition to wire bonding, the connection between the chip 12 and the substrate 10 can also be established by flip chip or controlled collapse chip connection (C4) with the formation of a bump. A resin 18 is used to seal the chip 12, and the electrical connection between the whole package and a printed circuit board can be achieved by ball grid array (BGA) which use solder balls 20 to connect the terminals on the printed circuit board. The drawback of this conventional multi-chip module is that a large surface is occupied since chips are packaged on the same side of surface. Therefore, the surface area of the package is large, and the signal path between chips is long. In addition, though the volume of the package can be reduced by using flip chip technique to achieve the connection between the chip and the carrier, the connection between chips still has to be achieved by the technique of printed circuits on the substrate 10. Therefore, it is not possible to effectively reduce signal transmission path and to shrink the volume or surface area at once. A low yield and a high cost are thus experienced in the prior art.
To further shrink the volume of package, a face to face multi-chip package is disclosed in U.S. Pat. No. 5,331,235. In FIG. 2, this multi-chip package comprises two chips 30 and 32 disposed face to face by way of tape automatic bonding (TAB). FIG. 2 illustrates inner lead bonding (ILB), whereby two chips 30, 32 having bumps 34, 36 are electrically connected to the film carrier 38. FIG. 2, further illustrates outer lead bonding (OLB), whereby the chips 30, 32 are connected to a lead frame 40. A solder ball 42 is formed between the chips 30, 32. The chips 30, 32, the film carrier 38 and the lead frame 40 are then molded with resin 44. This multi-chip package uses tape automatic bonding technique. The electrical connection between chips and printed circuit board is achieved by the installation of a lead frame or other carriers. The signal transmission path is lengthened. In addition, a film carrier is used to achieve the connection between chips, the layout of metal pad on the chips is formed by a line layout or a peripheral layout. Thus, the manners of line layout or peripheral layout can not meet the integration requirement for semiconductors with greatly increased number of input/output (I/O) nodes due to further higher integration.